In the semiconductor industry, it has become more and more difficult in recent years to improve device performance. Mobility enhancement is a known way to improve complementary metal oxide semiconductor (CMOS) device performance, without excessive device scaling. For example, it is known that the electron and hole mobility are affected by the wafer surface orientations as well as the current flow directions. This is because of the anisotropic effective mass behaviors of the inversion layer carriers.
Currently, CMOS devices are formed on a Si-containing semiconductor substrate that has a single crystal orientation. In a typical semiconductor substrate, the surface orientation is defined as the surface normal vector out of the crystal plane of the semiconductor wafer. The current direction of a CMOS can be designed at device layout. Under normal operation, the CMOS current always flows from the source to the drain side modulated by the gate terminal. Therefore, the current flow direction can be controlled by rotating the gate conductor mask and active silicon masks with respect to the wafer notch. Another way of changing the channel direction is to rotate the wafer at 45 degrees and have the notch along <100> instead of <110> direction.
In one example, CMOS devices can be formed upon a Si-containing substrate having a (100) surface orientation, i.e., crystal plane, with a notch or wafer flat located at the <110> direction. Such a Si-containing wafer is shown in FIG. 1; in this figure G represents the gate, S represents the source region, D represents the drain region and the bolded arrow represents the direction of current flow. In the illustrated Si-containing semiconductor wafer, the current flow is the <110> direction for both nFETs and pFETs. For a (100) oriented semiconductor wafer, the current flow is typically insensitive to the current flow directions, if the gates are laid out either parallel or perpendicular to the wafer notch.
Another way of increasing the device performance is to induce a local mechanical stress upon the channel of the CMOS devices. In some technologies, the local mechanical stress created in the channel can degrade the carrier mobility and cause layout related performance variations. Moreover, the optimal stress type and direction with respect to current flow direction is different for nFETs and pFETs. Furthermore, the optimal stress type and current direction for nFETs and pFETs are not compatible with the requirements for advanced litho where the gates are oriented in one direction.
Recently, studies have shown that nFET devices on a 45° rotated (100) semiconductor wafer (in which the channel is along the <100> direction) could be more sensitive to a uniaxial stress effect (See, FIG. 2). Also, it has been shown that pFETs on rotated wafers could have higher performance than those on non-rotated wafers because of higher hole mobility. Furthermore, holes are less sensitive to the transverse compressive stress induced by a stress induced shallow trench isolation region, thus in such structures including a rotated wafer there is less performance degradation compared to a normal wafer.
Despite these advances, there is a need for providing strained CMOS structures, particularly strained pFETs, on rotated semiconductor wafers to improve the device performance and to couple that with local mechanical stress to improve the electron and/or hole mobility in the channel of the particular CMOS structure.